Channel 0 configure register 1
TX_START | Set this bit to start sending data on CHANNEL%s. |
RX_EN | Set this bit to enable receiver to receive data on CHANNEL%s. |
MEM_WR_RST | Set this bit to reset write ram address for CHANNEL%s by accessing receiver. |
MEM_RD_RST | Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. |
APB_MEM_RST | Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. |
MEM_OWNER | This register marks the ownership of CHANNEL%s’s ram block. 1’h1: Receiver is using the ram. 1’h0: Transmitter is using the ram. |
TX_CONTI_MODE | Set this bit to restart transmission from the first data to the last data in CHANNEL%s. |
RX_FILTER_EN | This is the receive filter’s enable bit for CHANNEL%s. |
RX_FILTER_THRES | Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). |
CHK_RX_CARRIER_EN | Set this bit to enable memory loop read mode when carrier modulation is enabled for channel %s. |
REF_ALWAYS_ON | This bit is used to select the base clock for CHANNEL%s. 1’h1: clk_apb 1’h0:clk_ref |
IDLE_OUT_LV | This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. |
IDLE_OUT_EN | This is the output enable-control bit for CHANNEL%s in IDLE state. |
TX_STOP | Set this bit to stop the transmitter of CHANNEL%s sending data out. |